1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to a method and apparatus for quickly parsing a packet.
2. Related Art
Parsers are generally used to determine data portions of interest in a sequence of bits. Typically, the bits are examined according to a pre-specified convention (protocol) to determine the data portions of interest. For example, a parser may be used in a router (example of a device) to determine data portions such as destination address and type of service parameters in a received IP packet as is well known in the relevant arts.
In a prior approach, a device may implement a parser substantially in the form of software instructions in which the bits are generally examined sequentially according to a protocol to determine the specific bits of interest. For example, when parsing an IP packet, a parser may first examine the IP version number (e.g., version 4 or 6) and a header length to determine the specific bit positions at which a destination port number of interest is present.
One problem with such software implementations is that it may take a long time (or a large number of clock cycles) to parse data bits. Such long duration for parsing may be unacceptable in many environments. For example, with high speed technologies such as those based on optical fibre, packets may be received at a high frequency and it may be necessary to parse packets quickly (e.g., at “wire-speed”). Otherwise, the long parsing times may impede the throughput performance of a device processing the packets and the resulting long parsing times may be undesirable.
Therefore, what is needed are method and apparatus for parsing packets quickly.